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| White Electronic Designs 512Kx8 Plastic Monolithic SRAM CMOS FEATURES 512Kx8 bit CMOS Static Random Access Memory * Access Times of 17, 20, 25ns * Data Retention Function (LPA version) * Extended Temperature Testing * Data Retention Functionality Testing 36 lead JEDEC Approved Revolutionary Pinout * Plastic SOJ (Package 319) Single +5V (10%) Supply Operation EDI88512CA-RP WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to capitalize on the cost advantage of using a plastic component while not sacrificing all of the reliability available in a full military device. Extended temperature testing is performed with the test patterns developed for use on WEDC's fully compliant 512Kx8 SRAMs. WEDC fully characterizes devices to determine the proper test patterns for testing at temperature extremes. This is critical because the operating characteristics of device change when it is operated beyond the commercial guarantee a device that operates reliably in the field at temperature extremes. Users of WEDC's ruggedized plastic benefit from WEDC's extensive experience in characterizing SRAMs for use in military systems. WEDC ensures Low Power devices will retain data in Data Retention mode by characterizing the devices to determine the appropriate test conditions. This is crucial for systems operating at -40C or below and using dense memories such as 512Kx8s. WEDC's ruggedized plastic SOJ is footprint compatible with WEDC's full military ceramic 36 pin SOJ. FIG. 1 - PIN CONFIGURATION PIN Description TOP VIEW A0 A1 A2 A3 A4 CS# I/O0 I/O1 VCC VSS I/O2 I/O3 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE# I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O0-7 A0-18 WE# CS# OE# Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V 10%) Ground BLOCK DIAGRAM VCC VSS 36pin Revolutionary NC Memory Array Not Connected AO-18 Address Buffer Address Decoder I/O Circuits I/OO-7 WE# CS# OE# May 2004 Rev. 6 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ 0 to +70 -40 to +85 -55 to +125 -65 to +150 1.5 20 175 C C C C W mA C -0.5 to 7.0 Unit V OE# X H L X CS# H L L L WE# X H H L EDI88512CA-RP TRUTH TABLE Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 VCC + 0.5 +0.8 Unit V V V V NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAPACITANCE TA = +25C Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VIN = Vcc or Vss, f = 1.0MHz Max 6 8 Unit pF pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS VCC = 5V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current Operating Supply Current Standby Current Output High Volltage Output Low Voltage Symbol ILI ILO ICC ISB VOH VOL Conditions VCC = 5.5, VIN = VSS to VCC CS# = VIL, OE# = VIH, VOUT = VSS to VCC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOH = -4.0mA, VCC = 4.5 IOL = 8.0mA, VCC = 4.5 2.4 0.4 Min Max 10 10 180 15 Units A A mA mA V V NOTE: DC test conditions: VIL = 0.3V, VIH = VCC -0.3V AC TEST CONDITIONS Figure 1 Vcc Figure 2 Vcc 480 480 Q 255 30pF Q 255 5pF Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF (Figure 2) May 2004 Rev. 6 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC CHARACTERISTICS - READ CYCLE VCC = 5.0V, VSS = 0V, 0C TA +70C Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) 1. This parameter is guaranteed by design but not tested. EDI88512CA-RP Symbol JEDEC Alt. tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ 17ns Min 17 17 17 3 0 0 8 0 0 7 0 0 7 3 0 0 Max Min 20 20ns Max Min 25 20 20 3 8 0 0 10 0 8 0 25ns Max Units ns 25 25 ns ns ns 10 ns ns 12 ns ns 10 ns AC CHARACTERISTICS - WRITE CYCLE VCC = 5.0V, VSS = 0V, 0C TA +70C Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) 1. This parameter is guaranteed by design but not tested. Symbol JEDEC Alt. tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ 17ns Min 17 14 14 0 0 14 14 14 14 0 0 0 0 0 8 8 0 8 Max Min 20 15 15 0 0 15 15 15 15 0 0 0 0 0 10 10 0 20ns Max Min 25 17 17 0 0 17 17 17 17 0 0 0 0 8 0 12 12 0 25ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns ns ns ns May 2004 Rev. 6 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 2 - TIMING WAVEFORM -- READ CYCLE EDI88512CA-RP tAVAV ADDRESS tAVQV CS# tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tELQV tELQX OE# tEHQZ tAVQV DATA I/O tAVQX DATA 1 DATA 2 tGLQV tGLQX DATA OUT tGHQZ READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) READ CYCLE 2 (WE# HIGH) FIG. 3 - WRITE CYCLE -- WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH CS# tWHAX tAVWL WE# tWLWH tDVWH tWHDX DATA IN DATA VALID tWLQZ DATA OUT HIGH Z tWHQX WRITE CYCLE 1, WE# CONTROLLED FIG. 4 - WRITE CYCLE -- CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH CS# WS32K32-XHX tEHAX tAVEL WE# tWLEH tDVEH tEHDX DATA IN DATA OUT HIGH Z DATA VALID WRITE CYCLE 2, CS# CONTROLLED May 2004 Rev. 6 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs -55C TA +125C Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VDD ICCDR TCDR TR Conditions VDD = 2.0V CS# VDD -0.2V VIN VDD -0.2V or VIN 0.2V Min 2 - 0 TAVAV EDI88512CA-RP DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY) Typ - - - Max - 2 - - Units V mA ns ns FIG. 5 - DATA RETENTION - CS# CONTROLLED Data Retention Mode Vcc 4.5V VDD 4.5V tCDR CS# CS# = VDD -0.2V tR DATA RETENTION, CS# CONTROLLED May 2004 Rev. 6 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 6 - NORMALIZED OPERATING GRAPHS EDI88512CA-RP ICC1 (20ns) vs Temp 14 13 Write Pulse Width (ns) Write Pulse Width vs. Temp. 220 210 ICC1 (ma) 12 11 10 9 8 7 6 200 190 180 170 160 -55 25 Temp. (C) 125 -55 Temp. (C) 25 125 ICC3 vs. Temp 10 TAVQV (ns) ICC3 (ma) TAVQV vs. Temp 22 20 18 190 16 14 1 0.1 0.01 12 -55 25 Temp. (C) 125 -55 25 Temp. (C) 125 ICCDR vs. Temp 10 Normalized curves are offered as a service to our customers. They are not to be construed as a guarantee of operating characterics. Characteristics of actual devices will vary. 1 ICCDR (ma) 0.1 0.01 0.001 -55 25 Temp. (C) 125 IDR, 2V IDR, 3V May 2004 Rev. 6 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs EDI88512CA-RP PACKAGE 319: 36 LEAD, PLASTIC SMALL OUTLINE J-LEAD (SOJ) 0.920 0.930 0.395 0.405 0.360 0.435 0.380 0.445 0.027 min. Pin 1 Indicator 0.026 0.032 0.148 max. 0.375 TYP. 0.050 TYP. 0.015 0.021 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION EDI 8 8 512 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: M = 36 lead Plastic SOJ DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C May 2004 Rev. 6 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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